`ifdef ysyx_050369_SOC
module ysyx_050369 (
    input           clock,
    input           reset,
    input           io_interrupt,
    input           io_master_awready, 
    output          io_master_awvalid, 
    output [3:0]    io_master_awid,    
    output [31:0]   io_master_awaddr, 
    output [7:0]    io_master_awlen, 
    output [2:0]    io_master_awsize, 
    output [1:0]    io_master_awburst, 
    input           io_master_wready, 
    output          io_master_wvalid, 
    output [63:0]   io_master_wdata,   
    output [7:0]    io_master_wstrb,   
    output          io_master_wlast,   
    output          io_master_bready,  
    input           io_master_bvalid,  
    input [3:0]     io_master_bid,     
    input [1:0]     io_master_bresp,   
    input           io_master_arready, 
    output          io_master_arvalid, 
    output [3:0]    io_master_arid,    
    output [31:0]   io_master_araddr,  
    output [7:0]    io_master_arlen,   
    output [2:0]    io_master_arsize,  
    output [1:0]    io_master_arburst, 
    output          io_master_rready, 
    input           io_master_rvalid,  
    input [3:0]     io_master_rid,     
    input [1:0]     io_master_rresp,   
    input [63:0]    io_master_rdata,   
    input           io_master_rlast,   
    output          io_slave_awready, 
    input           io_slave_awvalid,
    input [3:0]     io_slave_awid,    
    input [31:0]    io_slave_awaddr,  
    input [7:0]     io_slave_awlen,   
    input [2:0]     io_slave_awsize, 
    input [1:0]     io_slave_awburst, 
    output          io_slave_wready,  
    input           io_slave_wvalid,  
    input [63:0]    io_slave_wdata,   
    input [7:0]     io_slave_wstrb,   
    input           io_slave_wlast,   
    input           io_slave_bready,  
    output          io_slave_bvalid,  
    output [3:0]    io_slave_bid,     
    output [1:0]    io_slave_bresp,   
    output          io_slave_arready, 
    input           io_slave_arvalid, 
    input [3:0]     io_slave_arid,    
    input [31:0]    io_slave_araddr,  
    input [7:0]     io_slave_arlen,   
    input [2:0]     io_slave_arsize,  
    input [1:0]     io_slave_arburst, 
    input           io_slave_rready,  
    output          io_slave_rvalid,  
    output [3:0]    io_slave_rid,     
    output [1:0]    io_slave_rresp,   
    output [63:0]   io_slave_rdata,   
    output          io_slave_rlast,
    output [5:0]    io_sram0_addr,
    output          io_sram0_cen,
    output          io_sram0_wen,
    output [127:0]  io_sram0_wmask,
    output [127:0]  io_sram0_wdata,
    input [127:0]   io_sram0_rdata,
    output [5:0]    io_sram1_addr,
    output          io_sram1_cen,
    output          io_sram1_wen,
    output [127:0]  io_sram1_wmask,
    output [127:0]  io_sram1_wdata,
    input [127:0]   io_sram1_rdata,
    output [5:0]    io_sram2_addr,
    output          io_sram2_cen,
    output          io_sram2_wen,
    output [127:0]  io_sram2_wmask,
    output [127:0]  io_sram2_wdata,
    input [127:0]   io_sram2_rdata,
    output [5:0]    io_sram3_addr,
    output          io_sram3_cen,
    output          io_sram3_wen,
    output [127:0]  io_sram3_wmask,
    output [127:0]  io_sram3_wdata,
    input [127:0]   io_sram3_rdata,
    output [5:0]    io_sram4_addr,
    output          io_sram4_cen,
    output          io_sram4_wen,
    output [127:0]  io_sram4_wmask,
    output [127:0]  io_sram4_wdata,
    input [127:0]   io_sram4_rdata,
    output [5:0]    io_sram5_addr,
    output          io_sram5_cen,
    output          io_sram5_wen,
    output [127:0]  io_sram5_wmask,
    output [127:0]  io_sram5_wdata,
    input [127:0]   io_sram5_rdata,
    output [5:0]    io_sram6_addr,
    output          io_sram6_cen,
    output          io_sram6_wen,
    output [127:0]  io_sram6_wmask,
    output [127:0]  io_sram6_wdata,
    input [127:0]   io_sram6_rdata,
    output [5:0]    io_sram7_addr,
    output          io_sram7_cen,
    output          io_sram7_wen,
    output [127:0]  io_sram7_wmask,
    output [127:0]  io_sram7_wdata,
    input [127:0]   io_sram7_rdata  
);
    assign io_slave_awready = 'b0;
    assign io_slave_wready  = 'b0;    
    assign io_slave_bvalid  = 'b0;   
    assign io_slave_bid     = 'b0;         
    assign io_slave_bresp   = 'b0;    
    assign io_slave_arready = 'b0;  
    assign io_slave_rvalid  = 'b0;   
    assign io_slave_rid     = 'b0;       
    assign io_slave_rresp   = 'b0;     
    assign io_slave_rdata   = 'b0;    
    assign io_slave_rlast   = 'b0;  
    wire          clk;
    wire          rst;   
    assign clk = clock;
    assign rst = reset;  
`else
module ysyx_22050369_cpu (
    input           clk,
    input           rst

);
    wire            io_interrupt;
    wire            io_master_awready; 
    wire            io_master_awvalid; 
    wire   [3:0]    io_master_awid;;    
    wire   [31:0]   io_master_awaddr; 
    wire   [7:0]    io_master_awlen; 
    wire   [2:0]    io_master_awsize; 
    wire   [1:0]    io_master_awburst; 
    wire            io_master_wready; 
    wire            io_master_wvalid; 
    wire   [63:0]   io_master_wdata;   
    wire   [7:0]    io_master_wstrb;   
    wire            io_master_wlast;   
    wire            io_master_bready;  
    wire            io_master_bvalid;  
    wire  [3:0]     io_master_bid;     
    wire  [1:0]     io_master_bresp;   
    wire            io_master_arready; 
    wire            io_master_arvalid; 
    wire   [3:0]    io_master_arid;    
    wire   [31:0]   io_master_araddr;  
    wire   [7:0]    io_master_arlen;   
    wire   [2:0]    io_master_arsize;  
    wire   [1:0]    io_master_arburst; 
    wire            io_master_rready; 
    wire            io_master_rvalid;  
    wire  [3:0]     io_master_rid;     
    wire  [1:0]     io_master_rresp;   
    wire  [63:0]    io_master_rdata;   
    wire            io_master_rlast; 
`endif
 
    wire [31:0] metvc;
    wire [31:0] mepc;
    wire        timer_valid;
    wire [31:0] pre_pc;
    wire        pre_jump;
    wire [31:0] pc;
    wire [31:0] nxpc;
    wire        pc_stop;
    wire icache_stop;
    wire        jump_valid;
    wire [3:0]  ready_ctrl;
    wire [3:0]  valid_ctrl;
    wire [1:0]  ex_fence_flag;
    wire wb_fence_flag;
    wire dc_fdone;
    ysyx_050369_pc_reg  pc_reg(
        .clk        (clk),
        .rst        (rst),
        .nxpc       (ctrl2pc_nxpc),
        .pc_stop    (pc_stop),
        .ex_fence_flag(ex_fence_flag[1]),
        .jump_valid (jump_valid),
        .pre_jump   (pre_jump),  
        .pre_pc     (pre_pc),
        .pc         (pc)
    );

    wire [31:0]     if2id_inst;
    wire [31:0]     if2id_pc;
    wire            if2id_valid;
    
    wire [31:0]     if2id_pre_pc;
    wire            if2id_pre_jump;
    wire   [127:0]  ic_cache_wdata;
    wire            ic_cache_wen;
    wire            ic_axi_read;
    wire            ic_unbrust;
    wire   [31 :0]  ic_raddr;
    wire ctrl_pc_error;
    ysyx_050369_if ifu(
        .clk           (clk),
        .rst           (rst),
        .pc_reg        (pc),
        .pre_pc        (pre_pc),
        .pre_jump      (pre_jump),
        .i_ctrl_pc_error(ctrl_pc_error),
        .if_valid      (valid_ctrl[3]),
        // .id2if_ready(id2if_ready),
        .i_pc_stop     (pc_stop),
        .o_inst        (if2id_inst),
        .o_pc_reg      (if2id_pc),
        .if2id_valid   (if2id_valid),
        .o_pre_pc      (if2id_pre_pc),
        .o_pre_jump    (if2id_pre_jump),
        .i_ex_fence_i  (ex_fence_flag[1]),
        .dc_fdone      (dc_fdone),
        .o_icache_stop (icache_stop),
`ifdef ysyx_050369_SOC
        .io_sram4_addr  (io_sram4_addr),
        .io_sram4_cen   (io_sram4_cen),
        .io_sram4_wen   (io_sram4_wen),
        .io_sram4_wmask (io_sram4_wmask),
        .io_sram4_wdata (io_sram4_wdata),
        .io_sram4_rdata (io_sram4_rdata),
        .io_sram5_addr  (io_sram5_addr),
        .io_sram5_cen   (io_sram5_cen),
        .io_sram5_wen   (io_sram5_wen),
        .io_sram5_wmask (io_sram5_wmask),
        .io_sram5_wdata (io_sram5_wdata),
        .io_sram5_rdata (io_sram5_rdata),
        .io_sram6_addr  (io_sram6_addr),
        .io_sram6_cen   (io_sram6_cen),
        .io_sram6_wen   (io_sram6_wen),
        .io_sram6_wmask (io_sram6_wmask),
        .io_sram6_wdata (io_sram6_wdata),
        .io_sram6_rdata (io_sram6_rdata),
        .io_sram7_addr  (io_sram7_addr),
        .io_sram7_cen   (io_sram7_cen),
        .io_sram7_wen   (io_sram7_wen),
        .io_sram7_wmask (io_sram7_wmask),
        .io_sram7_wdata (io_sram7_wdata),
        .io_sram7_rdata (io_sram7_rdata),
`endif 
        .cache_wdata    (ic_cache_wdata),
        .cache_wen      (ic_cache_wen),
        .axi_read       (ic_axi_read),
        .unbrust        (ic_unbrust),
        .ic_raddr       (ic_raddr)
    );

    wire  [4 :0]  rs1;
    wire  [4 :0]  rs2;
    wire  [4 :0]  rd;
    wire          RegWr;
    wire          ALUAsrc;
    wire   [2:0]  ALUBsrc;
    wire   [5:0]  ALUctr ;
    wire   [2:0]  Branch ;
    wire          MemtoReg ;
    wire          MemWr ;
    wire   [63:0] imm;
    wire   [7:0]  rmask;
    wire   [7:0]  wmask;

    wire        id2ex_csr_wen;
    wire        id2ex_valid;
    wire [31:0] id2ex_pc;
    wire [31:0] id2ex_inst;
    wire [31:0] id2ex_pre_pc;
    wire        id2ex_pre_jump;
    ysyx_050369_id    idu(
        .clk        (clk),
        .rst        (rst),
        .i_pc       (if2id_pc),
        .i_inst     (if2id_inst),
        .i_ex_fence_i(ex_fence_flag[1]),
        .i_pre_pc   (if2id_pre_pc),
        .i_pre_jump (if2id_pre_jump),
        .o_pre_pc   (id2ex_pre_pc),
        .o_pre_jump (id2ex_pre_jump),
    //from  ctrl
        .id_ready   (ready_ctrl[3]),
        .id_valid   (valid_ctrl[2]),
    //form ex
    //form if
        .if2id_valid (if2id_valid),
        .id2ex_valid (id2ex_valid),

        .o_pc       (id2ex_pc),
        .o_inst     (id2ex_inst),
        .o_rs1      (rs1),
        .o_rs2      (rs2),
        .o_rd       (rd),
        .o_RegWr    (RegWr),
        .o_ALUAsrc  (ALUAsrc),
        .o_ALUBsrc  (ALUBsrc),
        .o_ALUctr   (ALUctr),
        .o_Branch   (Branch),
        .o_MemtoReg (MemtoReg),
        .o_MemWr    (MemWr),
        .o_imm      (imm),
        .o_wmask    (wmask),
        .o_rmask    (rmask),
        .o_csr_wen  (id2ex_csr_wen )
    );
    wire reg_busy;
    // wire wb_reg_wen;
    // wire [4:0] wb_reg_waddr;
    wire ex2trl_jump_valid;
    wire [31:0] ctrl2pc_nxpc;
    wire          ALU_busy;
    // wire        wb_csr_wen ;
    // wire [11:0] wb_csr_waddr;



 


    wire [63 :0]src1;
    wire [63 :0]src2;
    wire [63 :0]wb2ex_src1;
    wire [63 :0]wb2ex_src2;
    wire          reg_wen;
    wire  [4 :0]  reg_waddr;
    wire  [63:0]  reg_res;
    wire          ex_csr_wen;
    wire  [11:0]  ex_csr_waddr;
    wire  [63:0]  ex_csr_wdata;
    wire  [63:0]  csr_rdata;

    wire          raise_intr;

    // wire          time_intr;
    wire          mem_wen;
    wire  [31:0]  mem_waddr;
    wire  [63:0]  mem_wdata;
    wire  [31:0]  mem_raddr;
    // wire  [63:0]  mem_rdata;
    wire  [7 :0]  mem_wmask;
    wire  [7 :0]  mem_rmask;
    wire          mem_ren;
    wire ex2as_valid;
    wire [31:0]ex2as_pc,ex2as_inst;
    wire pre_error;
    wire timer_flag;
    wire ex_mret_flag;
    wire ex_ecall_flag;
    ysyx_050369_ex exu(
        .clk        (clk),
        .rst        (rst),
        .ex_valid   (valid_ctrl[1]),
        .ex_ready   (ready_ctrl[2]),
        .o_ex_fence_i(ex_fence_flag),
        .i_dcache_done(dc_fdone),
        .ex2as_valid(ex2as_valid),
        .id2ex_valid(id2ex_valid),
        .o_mret_flag(ex_mret_flag),
        .o_ecall_flag(ex_ecall_flag),
        // .ex2id_ready(ex2id_ready), 

        .i_pc       (id2ex_pc),
        .i_inst     (id2ex_inst),
        .i_pre_pc   (id2ex_pre_pc),
        .i_pre_jump (id2ex_pre_jump),
        .pre_error  (pre_error),

        //from id
        // .i_op       (op),
        .i_src1     (src1),
        .i_src2     (src2), 
        .i_reg_waddr(rd),
        // .i_ExtOP    (ExtOP),
        .i_RegWr    (RegWr),
        .i_ALUAsrc  (ALUAsrc),
        .i_ALUBsrc  (ALUBsrc),
        .i_ALUctr   (ALUctr),
        .i_Branch   (Branch),
        .i_MemtoReg (MemtoReg),
        .i_MemWr    (MemWr),
        .i_imm      (imm),
        .i_wmask    (wmask),
        .i_rmask    (rmask),
        .i_csr_wen  (id2ex_csr_wen),
        .o_pc       (ex2as_pc),
        .o_inst     (ex2as_inst),
        //to reg-file

        .o_reg_wen  (reg_wen),
        .o_reg_waddr(reg_waddr),
        .o_reg_res  (reg_res),
        .o_ALU_busy (ALU_busy),
        //to csr_reg
        .i_csr_rdata(csr_rdata),
        .o_csr_wen  (ex_csr_wen),
        .o_csr_waddr(ex_csr_waddr),
        .o_csr_wdata(ex_csr_wdata),

        //to pc
        .o_jump_valid(ex2trl_jump_valid),
        .o_nxpc     (nxpc),
        .o_mem_wen  (mem_wen),
        .o_mem_waddr(mem_waddr),
        .o_mem_wdata(mem_wdata),
        .o_mem_wmask(mem_wmask),
        .o_mem_raddr(mem_raddr),
        .o_mem_ren  (mem_ren),
        .o_mem_rmask(mem_rmask)
        // .time_data_vaild(time_data_vaild),
        
    );
    wire as2wb_valid;
    // wire wb2as_ready;
    wire [63:0] as2wb_mem_rdata;
    wire [31:0] as2wb_mem_raddr;
    wire        as2wb_mem_ren;
    wire [63:0] as2wb_reg_wdata;
    wire        as2wb_reg_wen;
    wire [4:0]  as2wb_reg_waddr;
    wire [31:0] as2wb_inst;
	wire [2:0]  dc_size_t;
    wire        dc_axi_read;
    wire        dc_unbrust;
    wire        dc_uncache;
    wire [31:0] dc_raddr;
    wire [31:0] dc_waddr;
    wire [7 :0] dc_wstrb_t;
    wire  		dc_axi_write;
    wire [31:0] dc_dirty_addr;
    wire [127:0]dc_wdata;
    wire [127:0]dc_axi_data;
    wire        dc_axi_wen;
    wire        dc_wdone;
    wire        dc_rdone;
    wire            as0_wen;
    wire [4:0]      as0_waddr;
    wire [63:0]     as0_wdata;
    wire            as0_memren;
    wire [31:0]     as0_memaddr;
    wire [7 :0]     as0_memmask;
    wire            as0_memwen;
    wire [127:0]    cache_data;
    wire  [31:0]    cache_addr;
    wire            as1_wen;
    wire [4:0]      as1_waddr;
    wire [63:0]     as1_wdata;
    wire            as1_memren;
    wire            as2wb_dev;
    wire            dcache_stop; 
`ifndef ysyx_050369_SOC
    wire [31:0] as2wb_pc;
`endif 
    ysyx_050369_as as(
        .clk            (clk),
        .rst            (rst),
        .as_valid       (valid_ctrl[0]),
        .as_ready       (ready_ctrl[1]),
        .ex2as_valid    (ex2as_valid),
        .as2wb_valid    (as2wb_valid),
        .i_wb_fence     (wb_fence_flag),
        .o_fdone        (dc_fdone),
        .i_pc           (ex2as_pc),
        .i_inst         (ex2as_inst),
        .i_reg_wen      (reg_wen),
        .i_reg_waddr    (reg_waddr),
        .i_reg_res      (reg_res),   
        .i_mem_wen      (mem_wen),
        .i_mem_waddr    (mem_waddr),
        .i_mem_wdata    (mem_wdata),
        .i_mem_wmask    (mem_wmask),
        .i_mem_ren      (mem_ren),
        .i_mem_raddr    (mem_raddr),
        .i_mem_rmask    (mem_rmask),
        .i_ctreg_data   (ctreg_data),
        .o_inst         (as2wb_inst),
        .o_mem_rdata    (as2wb_mem_rdata),
        .o_mem_raddr    (as2wb_mem_raddr),
        .o_mem_ren      (as2wb_mem_ren),
        .o_reg_wdata    (as2wb_reg_wdata),
        .o_reg_wen      (as2wb_reg_wen),
        .o_reg_waddr    (as2wb_reg_waddr),
        .o_as0_wen      (as0_wen),
        .o_as0_waddr    (as0_waddr),
        .o_as0_wdata    (as0_wdata),
        .o_as0_memren   (as0_memren),
        .o_as0_memaddr  (as0_memaddr),
        .o_as0_memmask  (as0_memmask),
        .o_as0_memwen   (as0_memwen),
        .o_cache_data   (cache_data),
        .as2wb_dev      (as2wb_dev),
`ifdef ysyx_050369_SOC
        .io_sram0_addr  (io_sram0_addr),
        .io_sram0_cen   (io_sram0_cen),
        .io_sram0_wen   (io_sram0_wen),
        .io_sram0_wmask (io_sram0_wmask),
        .io_sram0_wdata (io_sram0_wdata),
        .io_sram0_rdata (io_sram0_rdata),
        .io_sram1_addr  (io_sram1_addr),
        .io_sram1_cen   (io_sram1_cen),
        .io_sram1_wen   (io_sram1_wen),
        .io_sram1_wmask (io_sram1_wmask),
        .io_sram1_wdata (io_sram1_wdata),
        .io_sram1_rdata (io_sram1_rdata),
        .io_sram2_addr  (io_sram2_addr),
        .io_sram2_cen   (io_sram2_cen),
        .io_sram2_wen   (io_sram2_wen),
        .io_sram2_wmask (io_sram2_wmask),
        .io_sram2_wdata (io_sram2_wdata),
        .io_sram2_rdata (io_sram2_rdata),
        .io_sram3_addr  (io_sram3_addr),
        .io_sram3_cen   (io_sram3_cen),
        .io_sram3_wen   (io_sram3_wen),
        .io_sram3_wmask (io_sram3_wmask),
        .io_sram3_wdata (io_sram3_wdata),
        .io_sram3_rdata (io_sram3_rdata),
`else 
        .o_pc           (as2wb_pc),
`endif 
///////////////////////////
        .size_t         (dc_size_t),
        .axi_read       (dc_axi_read),
        .unbrust        (dc_unbrust),
        .uncache        (dc_uncache),
        .dc_raddr       (dc_raddr),
        .dc_waddr       (dc_waddr),
        .wstrb_t        (dc_wstrb_t),
        .axi_write      (dc_axi_write),
        .dirty_addr     (dc_dirty_addr),
        .dc_wdata       (dc_wdata),
        .i_axi_data     (dc_axi_data),
        .i_axi_wen      (dc_axi_wen),
        .wdone          (dc_wdone),
        .rdone          (dc_rdone),
        .axi_stop       (dcache_stop)
    );
    wire [63:0] ctreg_data;
    wire msip_valid;
    ysyx_050369_clint clint(
        .clk        (clk),
        .rst        (rst),
        .i_timer_valid (timer_valid),
        .pc_stop    (pc_stop),
        .mem_waddr  (mem_waddr),
        .mem_wdata  (mem_wdata),
        .mem_wmask  (mem_wmask[3:0]),
        .mem_wen    (mem_wen),
        .mem_raddr  (mem_raddr),
        .mem_rdata  (ctreg_data),
        .time_intr  (timer_flag),
        .msip_valid (msip_valid)
    );

    // wire [31:0]wb_pc_o,wb_inst_o;
    ysyx_050369_wb wb(
        .clk            (clk),
        .rst            (rst),
        .wb_ready       (ready_ctrl[0]),
        .as2wb_valid    (as2wb_valid),
        .i_inst         (as2wb_inst),
    `ifndef ysyx_050369_SOC
        .i_pc           (as2wb_pc),
        .i_dev          (as2wb_dev),
    `endif
        .i_reg_wdata    (as2wb_reg_wdata),
        .i_reg_wen      (as2wb_reg_wen),
        .i_reg_waddr    (as2wb_reg_waddr),
        .i_rs1          (rs1),
        .i_rs2          (rs2),
        .o_rd1          (wb2ex_src1),
        .o_rd2          (wb2ex_src2),
        .o_fence_i      (wb_fence_flag)
    );

ysyx_050369_csr_reg csr_reg(
    .clk        (clk),
    .rst        (rst),
    .csr_wen    (ex_csr_wen),
    .csr_waddr  (ex_csr_waddr),
    .csr_wdata  (ex_csr_wdata),
    .csr_raddr  (imm[11:0]),
    .csr_rdata  (csr_rdata),
    .i_ctime    (timer_flag)    ,   
    .i_cmsip    (msip_valid),
    .i_cext     (io_interrupt),
    .i_pc_stop  (pc_stop),
    .i_ecall_flag(ex_ecall_flag),
    .i_ecall_pc (ex2as_pc),
    .i_ex_nxpc  (nxpc),
    .o_metvc    (metvc),
    .o_mepc     (mepc),
    .timer_valid (timer_valid),
    .raise_intr (raise_intr),
    .mret_flag  (ex_mret_flag)
);
    ysyx_050369_reg_sb reg_sb( 
        .clk            (clk),
        .rst            (rst),
        .i_cache_data   (cache_data),
        .i_id_rs1       (rs1),
        .i_id_rs2       (rs2),
        .i_ex_wen       (reg_wen),
        .i_ex_waddr     (reg_waddr),
        .i_ex_wdata     (reg_res),
        .i_ex_mem2reg   (mem_ren),
        .i_ex_memraddr  (mem_raddr),
        .i_ex_memmask   (mem_rmask),
        .i_ex_memwen    (mem_wen),
        .i_as0_wen      (as0_wen),
        .i_as0_waddr    (as0_waddr),
        .i_as0_wdata    (as0_wdata),
        .i_as0_memren   (as0_memren),
        .i_as0_memraddr (as0_memaddr),
        .i_as0_memmask  (as0_memmask),
        .i_as0_memwen   (as0_memwen),
        .i_as1_wen      (as2wb_reg_wen),
        .i_as1_waddr    (as2wb_reg_waddr),
        .i_as1_wdata    (as2wb_reg_wdata),
        .i_as1_memren   (as2wb_mem_ren),
        .i_as1_memrdata (as2wb_mem_rdata),
        .i_as1_memraddr (as2wb_mem_raddr),
        .i_rd_1         (wb2ex_src1),
        .i_rd_2         (wb2ex_src2), 
        .o_rd1          (src1),
        .o_rd2          (src2),
        .reg_stop       (reg_busy)
    );   
    ysyx_050369_ctrl ctrl(
        .rst            (rst),
        .i_ex_fence     (ex_fence_flag[0]),
        .i_ecall_flag   (ex_ecall_flag),
        .i_mret_flag    (ex_mret_flag),
        .i_mepc         (mepc),
        .i_metvc        (metvc),
        .i_raise_intr   (raise_intr),
        .i_nxpc         (nxpc),
        .i_pre_error    (pre_error),
        .i_reg_busy     (reg_busy),
        .i_ALU_busy     (ALU_busy),
        .i_dcache_stop  (dcache_stop),
        .i_icache_stop  (icache_stop),
        .o_ready        (ready_ctrl), 
        .o_valid        (valid_ctrl),
        .o_jump_valid   (jump_valid),
        .o_nxpc         (ctrl2pc_nxpc),
        .o_pc_stop      (pc_stop),
        .o_pc_error     (ctrl_pc_error)

    );

ysyx_050369_pc_pre pc_pre(
        .clk            (clk),
        .rst            (rst),
        .i_if_pc        (pc),
        .i_pc_stop      (pc_stop),
        .i_ex_pc        (ex2as_pc),
        .i_jump_valid   (ex2trl_jump_valid),
        .i_nxpc         (ctrl2pc_nxpc),
        .i_pre_error    (pre_error),
        .o_jump_valid   (pre_jump),
        .o_pc_pre       (pre_pc)
);

ysyx_050369_axi_arbiter cache_arbiter(
    .clk            (clk),
    .rst            (rst),
    //ifu
    .o_ic_cache_wdata (ic_cache_wdata),
    .o_ic_cache_wen   (ic_cache_wen),
    .i_ic_axi_read    (ic_axi_read),
    .i_ic_unbrust     (ic_unbrust),
    .i_ic_raddr       (ic_raddr),
	.i_dc_size_t      (dc_size_t),
    .i_dc_axi_read    (dc_axi_read),
    .i_dc_unbrust     (dc_unbrust),
    .i_dc_uncache     (dc_uncache),
    .i_dc_raddr       (dc_raddr),
    .i_dc_waddr       (dc_waddr),
    .i_dc_wstrb_t     (dc_wstrb_t),
    .i_dc_axi_write   (dc_axi_write),
    .i_dc_dirty_addr  (dc_dirty_addr),
    .i_dc_wdata       (dc_wdata),
    .o_dc_axi_data    (dc_axi_data),
    .o_dc_axi_wen     (dc_axi_wen),
    .o_dc_wdone       (dc_wdone),
    .o_dc_rdone       (dc_rdone),
// slave
    //read addr
    .i_sl_arready   (io_master_arready),
    .o_sl_arvalid   (io_master_arvalid),
    .o_sl_araddr    (io_master_araddr),
    .o_sl_arid      (io_master_arid),
    .o_sl_arlen     (io_master_arlen),
    .o_sl_arsize    (io_master_arsize),
    .o_sl_arburst   (io_master_arburst),
    //read data
    .o_sl_rready    (io_master_rready),
    .i_sl_rvalid    (io_master_rvalid),
    .i_sl_rresp     (io_master_rresp),
    .i_sl_rdata     (io_master_rdata),
    .i_sl_rlast     (io_master_rlast),
    .i_sl_rid       (io_master_rid),
    //write addr
    .i_sl_awready   (io_master_awready),
    .o_sl_awvalid   (io_master_awvalid),
    .o_sl_awaddr    (io_master_awaddr),
    .o_sl_awid      (io_master_awid),
    .o_sl_awlen     (io_master_awlen),
    .o_sl_awsize    (io_master_awsize),
    .o_sl_awburst   (io_master_awburst),
    //write data
    .i_sl_wready    (io_master_wready),
    .o_sl_wvalid    (io_master_wvalid),
    .o_sl_wdata     (io_master_wdata),
    .o_sl_wstrb     (io_master_wstrb),
    .o_sl_wlast     (io_master_wlast),
    //write res
    .o_sl_bready    (io_master_bready),
    .i_sl_bvalid    (io_master_bvalid),
    .i_sl_bresp     (io_master_bresp),
    .i_sl_bid       (io_master_bid)
); 

`ifndef ysyx_050369_SOC
axi_slave slave(
    .clk        (clk),    // Clock
    .rst        (rst),  // Asynchronous reset active low
            //read addr
    .o_arready  (io_master_arready),
    .i_arvalid  (io_master_arvalid),
    .i_araddr   (io_master_araddr),
    .i_arid     (io_master_arid),
    .i_arlen    (io_master_arlen),
    .i_arsize   (io_master_arsize),
    .i_arburst  (io_master_arburst),
        //read data
    .i_rready   (io_master_rready),
    .o_rvalid   (io_master_rvalid),
    .o_rresp    (io_master_rresp),
    .o_rdata    (io_master_rdata),
    .o_rlast    (io_master_rlast),
    .o_rid      (io_master_rid),
        //write addr
    .o_awready  (io_master_awready),
    .i_awvalid  (io_master_awvalid),
    .i_awaddr   (io_master_awaddr),
    .i_awid     (io_master_awid),
    .i_awlen    (io_master_awlen),
    .i_awsize   (io_master_awsize),
    .i_awburst  (io_master_awburst),
        //write data
    .o_wready   (io_master_wready),
    .i_wvalid   (io_master_wvalid),
    .i_wdata    (io_master_wdata),
    .i_wstrb    (io_master_wstrb),
    .i_wlast    (io_master_wlast),
        //write res
    .i_bready   (io_master_bready),
    .o_bvalid   (io_master_bvalid),
    .o_bresp    (io_master_bresp),
    .o_bid      (io_master_bid)
    
);
`endif

// reg [31:0]stop_cnt[4:0];
// reg [31:0]dcache_cnt;
// reg [31:0]reg_busy_cnt;
// reg [31:0]pre_error_cnt;
// reg [31:0]ALU_stop_cnt;
// import "DPI-C" function void get_stop_cnt(input logic [31:0] a0[]);
// always @(posedge clk ) begin
//     if (rst) begin
//         // icache_cnt    <= 'b0;
//         // dcache_cnt    <= 'b0;
//         // reg_busy_cnt  <= 'b0;
//         // pre_error_cnt <= 'b0;
//         // ALU_stop_cnt  <= 'b0;
//         stop_cnt [0] <= 'b0;
//         stop_cnt [1] <= 'b0;
//         stop_cnt [2] <= 'b0;
//         stop_cnt [3] <= 'b0;
//         stop_cnt [4] <= 'b0;
//     end
//     else if (~pc_stop ) begin
//         if (pre_error) begin
//             stop_cnt [4] <= stop_cnt [4] +1;
//         end
//     end
//     else begin
//         if (dcache_stop) begin
//             stop_cnt [3] <= stop_cnt [3] +1;
//         end
//         if (icache_stop) begin
//             stop_cnt [2] <= stop_cnt [2] +1;
//         end
//         if (ALU_busy) begin
//             stop_cnt [1] <= stop_cnt [1] +1;
//         end
//         if (reg_busy) begin
//             stop_cnt [0] <= stop_cnt [0] +1;
//         end
//     end
// end
// always @(*) begin
//     get_stop_cnt(stop_cnt);
// end
endmodule